


module alu (
    input wire [31:0] a,
    input wire [31:0] b,
    input wire [2:0] f,
    output wire [31:0] s
  );
  always @(*) begin
    case (s)
      3'b000:begin
        s <= a + b;
      end
      3'b001: begin
        s <= a - b;
      end
      3'b010: begin
        s <= a & b;
      end
      3'b011: begin
        s <= a | b;
      end
      3'b100: begin
        s <= -a;
      end
      3'b101: begin
        s <= (a < b);
      end
      default: begin
        s <= 32'b0;
      end
    endcase
  end

  assign s = condition ? a : b;
endmodule

module alu_assign (
  input wire [31:0] a,
  input wire [31:0] b,
  input wire [2:0] f,
  output wire [31:0] s,
  output 
  );
  assign s = condition ? a : b;
endmodule